A general trend of modern day electronic products, as demanded by the market place, is product miniaturization with vastly increasing functionality. The same trend also applies to the segment of power electronics. Hence, in the area of power semiconductor devices there has been an ongoing need of product miniaturization concurrent with functional requirements of reduced device internal resistance and efficient heat dissipation.
As it offers advantages of bulk device electrical resistance reduction while maintaining a small package footprint, the ability of making and stacking multiple thin chips of power semiconductor devices has become very desirable in the semiconductor industry. The following is a brief review of some prior arts for making and stacking multiple chips.
FIG. 9 is an excerpted FIG. 2 from a U.S. patent application publication # 20090108469 entitled “CHIP STACK PACKAGE” by Sun-Won KANG; et al, hereinafter referred to as US 20090108469. As seen, the chip stack package 500 of US20090108469 includes a wiring substrate 10, a plurality of chips 100, and a plurality of adhesive layers 108, wherein the chips 100 are stacked and adhered to each other by the adhesive layers 108 as intermediary media on the wiring substrate 10 by using a wafer level or chip level process. The chips 100 are electrically coupled to each other using through via electrodes 102 that are formed through the chips 100 and electrically coupled to the wiring substrate 10. The chip 100 is formed on a silicon wafer, and the through via electrodes 102 are formed through the silicon wafer. External input/output (I/O) terminals 110, each of which may be shaped like a solder ball, are formed on a bottom surface of the wiring substrate 10. The adhesive layers 108 may each be an adhesive tape.
FIG. 10 is an excerpted FIG. 1 from a U.S. patent application publication # 20090135638 entitled “SEMICONDUCTOR MEMORY DEVICE CAPABLE OF IDENTIFYING A PLURALITY OF MEMORY CHIPS STACKED IN THE SAME PACKAGE” by Yuui Shimizu, hereinafter referred to as US20090135638. Specifically, FIG. 10 is a perspective view showing the structure of a multi-chip package structure memory device (semiconductor memory device) 100 according to a first embodiment of US20090135638. Four resistance-change memory chips (hereinafter, referred to as memory chips) 111A to 111D using a resistance-change memory element as a memory cell are stacked in the same package. The memory device 100 of this embodiment includes four memory chips 111A to 111D, which are successively stacked on a package substrate 101. These four memory chips 111A to 111D each have the same configuration (specification), and stacked so that they are mutually overlapped vertically as a whole. Each of the memory chips 111A to 111D is provided with a plurality of (nine in this embodiment) pads 121 to 129 and a chip address identification circuit 150. Of those pads 121 to 129, pads 121 and 122 are used as first and second memory position detection pad P1 (Vtest), and P2 (Vss) for recognizing a chip address, respectively. Other pads 123 to 129 are used as input/output (I/O), control, power supply (Vdd) and ground (Vss) pads, respectively. The pads 121 to 129 of each of memory chips 111A to 111D are mutually connected (short-circuited) using a through via (vertical via technique) 103. For example, the pad 121 is given as one example. The through via 103 connects between the pad 121 of the memory chip 111A and the pad 121 of the memory chip 111B, between the pad 121 of the memory chip 111B and the pad 121 of the memory chip 111C and between the pad 121 of the memory chip 111C and the pad 121 of the memory chip 111D. The pad 121 of the memory chip 111A is connected to the package substrate 101 via the lowermost through via 103. Although described later, the pads 121 to 129 of each of the memory chips 111A to 111D have a through silicon via structure (TSV). According to the through silicon via structure (TSV), the pads 121 to 129 have an electrode on each of chip front and backside surfaces. The first and second memory position detection pads 121 (P1) and 122 (P2) are short-circuited. According to this embodiment, the first and second memory position detection pads 121 (P1) and 122 (P2) are connected via a package frame conductor pattern 131 between the lowermost through vias 103 on the surface of the package substrate 101. Specifically, the first and second memory position detection pads 121 (P1) and 122 (P2) of the memory chips 111A to 111D are conducted using eight through vias 103 and one conductor pattern 131. Thus, a test voltage Vtest is applied to the first and second memory position detection pad 121 (P1) of the uppermost memory chip 111D from an external tester (not shown). The second memory position detection pads 122 (P2) of the memory chip 111D is connected to ground (Vss). In this way, a current flows from the first memory position detection pads 121 (P1) of the memory chip 111D to the second memory position detection pads 122 (P2). Although is not illustrated, the memory chips 111A to 111D on the package substrate 101 are sealed by a sealer such as resin at its surroundings except the pads 121 to 129 of the uppermost memory chip 111D.
In addition to the above, the following prior arts related to direct chip stacking are noted:                U.S. patents: U.S. Pat. Nos. 5,818,107, 6,002,177, 7,217,995, 7,446,420, 7,494,909, 7,507,637, 7,595,559, 7,598,617.        U.S. patent application publications: US20080157357, US20090032928, US20090209063, US20090261457, US20090001543, US20090065950, US20090160051, US20090020855.However the aforementioned prior arts are related to lateral devices which only have electrodes on the top side and do not show how to stack vertical semiconductor dies (especially power semiconductor devices) which have electrodes on both the top and the bottom. In view of the above prior arts, the present invention proposes a stackable power MOSFET structure for directly stacking power MOSFET devices (which have electrodes on both sides) to achieve high functional performance while limiting package footprint and size.        
FIG. 111 and FIG. 112 are respectively excerpted FIG. 3 and FIG. 4 from a U.S. patent application publication # 20080150105 entitled “Power Semiconductor Component Stack Using Lead Technology with Surface-Mountable External Contacts and a Method for Producing the Same” by Khalil Hosseini; et al, hereinafter referred to as US20080150105. Specifically, FIG. 11A shows a schematic, opened-up, perspective view of two MOSFET power semiconductor components 2 and 3 for a parallel-connected MOSFET power semiconductor component stack 30, which is shown in FIG. 11B. In this case, in the intermediate plane 14 for a parallel-connected MOSFET power semiconductor component stack, two source electrodes S are arranged congruently one above another, and two gate external contacts G are likewise aligned congruently with respect to one another. For a parallel circuit, the two source and the two gate external contacts in the intermediate plane 14 are aligned with one another and electrically connected to one another via a soldering layer. This then results in the MOSFET power semiconductor component stack 30 shown in FIG. 11B.
FIG. 11B shows a schematic, perspective view of a parallel-connected MOSFET power semiconductor component stack 30, which has a drain external contact D, a source external contact S and a gate external contact G on its top side. In this case, the gate external contact G and the source external contact are looped through via the intermediate plane 14 down to the underside 5 of the MOSFET power semiconductor component stack 30, while a conduction strip 32 is provided for the drain external contact D on the top side 13 of the MOSFET power semiconductor component stack 30 in order to lead the drain external contact D from the top side 13 of the MOSFET power semiconductor component stack 30 to the level of the underside 5 of the MOSFET power semiconductor component stack 30. If corresponding drain external contacts are also provided in addition to the source external contacts S and the gate external contacts G in the intermediate plane 14 as shown in FIG. 3, then the conduction strip 32 can be dispensed with in the case of a series circuit.
However US20080150105 only shows a way to stack MOSFETs at packaged component level. Also, it does not show how to easily stack more than two MOSFET components.
FIG. 12 illustrates a traditional MOSFET 10 with multiple interdigitated source-body regions 23a-23i and trenched gate regions 24a-24j built on top of a semiconductor substrate 21 with a bottom drain metal layer 22. In this example, the semiconductor substrate 21 may comprise of an epitaxial layer 21b over a heavily doped substrate layer 21a. The multiple source-body regions 23a-23i are in contact and parallely connected to a patterned source-body metal layer 25c. Likewise, although not shown here with connection specifics to avoid unnecessary obscuring details, the trenched gate regions 24a-24j are in contact and parallely connected to a patterned gate metal layer 26h beneath a top passivation 29. Note that the top source metal 25c and bottom drain metal 22 are located on opposite sides of the semiconductor device, which makes it difficult to stack such devices, especially when using through vias.